Taiwan Semiconductor Manufacturing Co (TSMC), the world’s leading chipmaker and the fabricator behind Nvidia’s advanced AI chips, has introduced a strategy to dramatically boost the energy efficiency of the processors central to artificial intelligence.
Unveiled at a Silicon Valley conference on Wednesday, TSMC showcased several innovations—including the adoption of AI-driven software to optimize chip design—that it expects will make AI computing chips up to ten times more energy efficient.
As demand mounts for ever-greater processing power, the issue of electricity consumption has come under scrutiny. Nvidia’s latest AI servers, for example, can draw as much as 1,200 watts during intensive workloads—the equivalent power consumption of 1,000 U.S. homes if sustained without interruption.
TSMC’s approach centers on a novel architecture that arranges multiple “chiplets”—smaller, specialized pieces of a larger chip—into a single computing module. This packaging leverages varied technologies to push the envelope on performance and energy use.
Rising chip complexity, however, is driving the need for smarter solutions in design. Accordingly, chip designers are increasingly turning to AI-powered software from companies such as Cadence Design Systems and Synopsys, both of which revealed new products on Wednesday after close collaboration with TSMC.
The impact of these tools is already apparent. For some of the most challenging design problems, AI-driven software developed by TSMC’s partners identified superior solutions and did so significantly faster than TSMC’s own experienced engineers.
Jim Chang, deputy director of TSMC’s 3DIC Methodology Group, highlighted during the conference presentation that leveraging AI-driven tools allows TSMC to fully realize its technological capabilities—a benefit he described as highly valuable. The software completes the task in five minutes, whereas the engineers would need two days to arrive at the same outcome, Chang noted.
The limitations of current chip manufacturing methods are also becoming clear, particularly when it comes to data transfer speeds via electrical connections. New approaches, such as using optical connections to move data between chips, will need to reach high levels of reliability before they can be widely adopted in large-scale data centers, according to Kaushik Veeraraghavan, an engineer in Meta Platforms’ infrastructure team, who delivered the keynote address.
